The present invention relates to error injection methods and apparatus used in the testing of electronic data processing systems, and more particularly relates to the injection of errors into a channel of an electronic data processing system and means to time the recovery of the system from the injected error.
As electronic data processing machines have become more sophisticated, tools and techniques for testing these data processing machines have become more sophisticated. Typically, testing tools have been external devices which depended upon stimuli such as electrical signals for indicating the state of the machine or portion of the machine being tested. Faults or errors are then injected in response to the stimuli to test machine's reaction to a fault in that particular state.
D. G. East et al., Error Injector for Testing a Data Processing Unit, IBM Technical Discl. Bulletin, vol. 17 no. 6, Nov. 1974, pp. 1691-1692, discloses a tool for injecting errors in which the unit under test produces a multibit signal which identifies the particular operations of the unit during the test. The multibit signal is compared by match logic which includes a set of manual switches to determine when an error is to be injected. The injector includes circuitry to delay the error injection for a set count after the multibit signal is matched, and circuitry to stop the error pulses after a preset count.
J. N. Gaulrapp et al., Error Injection Tool, IBM Technical Discl. Bulletin, vol. 20 no. 8, Jan. 1978, p. 3286, discloses an error injection tool for injecting error pulses into circuitry to test hardware and software error recovery. The disclosed tool includes a trigger circuit, which, when triggered, injects an error into a circuit under test after a user set number of counts have been received by a counter. The width of the injected error may also be set by a width counter.
E. J. Cerul et al., Synchronized Error Injection, IBM Technical Discl. Bulletin, vol. 24 no. 5, Oct. 1981, p 2331, discloses a reloadable control store in the director to establish error states in synchronism with central processor execution of an I/O related function. The reloadable control store contains control word microprograms for operating the director and may be loaded with a special control word for initiating a synchronized error injection mode of operation in the director.
U.S. Pat. No. 4,149,038 to Pitroda et al. for Method and Apparatus for Fault Detection and PCM Multiplexed System Apr. 10, 1979, and U.S. Pat. No. 4,393,490 to Culley for Digital Telecommunications Switches Network with In-Built Fault Identification issued Jul. 12, 1983. Both of these patents disclose telecommunications networks into which parity errors or error patterns are deliberately injected to find faults.
U.S. Pat. No. 4,719,626 to Ogasawara for Diagnostic Method and Apparatus for Channel Control Apparatus issued Jan. 12, 1988 and discloses a data processing system in which errors are sent to a pseudo-input/output control unit to test the common bus interface of a channel control. External errors are injected from an outside source into the functional channel unit to provide data for diagnostic purposes.
U.S. Pat. No. 6,759,019 to Bently et al. for Programmable Fault Injection Tool issued Jul. 19, 1988 and discloses an external tool for injecting faults into a system under test in response to sensed external hardware events to determine the state of the system under test. The disclosed tool includes a user interface to give parameters to a microprocessor which can be programmed to control tests of a system wherein the test is responsive to the sensed state of the system.
U.S. Pat. No. 4,779,271 to Suzuki for Forced Error Generating Circuit for a Data Processing Unit issued Oct. 18, 1988 and discloses an external circuit for generating errors for a data processing unit responsive to a signal for starting a period for causing the error and a forced error generating instruction.